There has been known a semiconductor integrated circuit including: a CPU; a clock generation circuit; and a power supply circuit (see Patent Document 1). The clock generation circuit supplies an operational clock signal to the CPU. The CPU specifies a frequency of the operational clock signal for the clock generation circuit and specifies an internal power supply voltage for the power supply circuit. The power supply circuit includes: a voltage regulator to generate an internal power supply voltage from an external power supply voltage; and a determination circuit to determine a transition state to the specified internal power supply voltage. The determination circuit receives input of a first signal output from the CPU and then determines attainment to the specified internal power supply voltage to output a second signal to the CPU.
Further, there has been known a semiconductor device including a source voltage detection circuit that is attached on a system clock generation circuit of a semiconductor integrated circuit so that a frequency of a CPU system clock can be automatically changed (see Patent Document 2).
Further, there has been known a semiconductor device including an oscillation unit that supplies an oscillated clock to a circuit included in the semiconductor device (see Patent Document 3). A frequency setting information storage unit stores a plurality of sets of frequency information indicating setting of a frequency supplied by the oscillation unit and frequency identification information identifying the frequency information and outputs one of a plurality of pieces of the frequency information to the oscillation unit based on frequency identification information input thereinto. A speed setting information storage unit stores speed identification information indicating a speed of the semiconductor device and frequency identification information corresponding to the speed identification information. A frequency identification information count unit holds a value of the frequency identification information input into the frequency setting information storage unit. A control unit causes the frequency identification information count unit to increment or decrement the held value of the frequency identification information to approach a value of the frequency identification information stored in the speed setting information storage unit.
[Patent Document 1] Japanese Laid-open Patent Publication No. 2003-330549
[Patent Document 2] Japanese Laid-open Patent Publication No. 06-4169
[Patent Document 3] Japanese Laid-open Patent Publication No. 2013-196619
When a frequency of a clock signal is changed not stepwise but greatly during the operation of a processor, a load greatly changes to cause a large power supply noise as a result. Therefore, when changing the frequency, it is preferred to perform control such as not to change it to a target value at once but to change it stepwise to the target value. However, when the frequency is changed stepwise, there is generated a problem that a time period for changing the frequency from a current frequency to a target frequency is prolonged.